K4S283233F-M rev. 0.8 nov. 2001 cmos sdram 4mx32 sdram revision 0.8 november 2001 (v dd /v ddq 3.0v/3.0v & 3.3v/3.3v) 90fbga
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram revision history revision 0.0 (march 26. 2001, preliminary) ? first generation for 4mx32 3.0v sdram fbga. revision 0.1 (may 3. 2001, preliminary) ? change of ioh and iol from -0.1ma and 0.1ma to -2ma and 2ma. revision 0.2 (may 18. 2001, preliminary) ? change of ball configuration in order to be compatible with jedec standard package in case of sequential operatin. ? ball location of a3, a11 and a7 is different from jedec standard. revision 0.3 (june 11. 2001, target) ? change of ball configuration in order to be compatible with jedec standard package perfectly. revision 0.4 (june 22. 2001, target) ? changed device name from low power sdram to mobile sdram. revision 0.5 (june 26. 2001, target) ? integration to K4S283233F-Mxxx of 3.0v and 3.3v part. ? integration to -1l code of -1l and -15 code. revision 0.6 (july 12. 2001, target) ? addition of -1h part specification. ? change tsh for 100mhz, cl3 part from 1.5ns to 1ns. revision 0.7 (july 12. 2001, preliminary) ? reduction of dc current. revision 0.8 (november 1. 2001, final) ? 4mx32 final specification.
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram general description features 1m x 32bit x 4 banks sdram in 90fbga functional block diagram ordering information part no. max freq. interface package K4S283233F-Me/n75 133mhz(cl=3) 100mhz(cl=2) lvttl 90 balls fbga K4S283233F-Me/n1h 100mhz(cl=2) K4S283233F-Me/n1l 100mhz(cl=3) *1 - me ; normal power, extended temperature. - mn ; low power, extended temperature. 1. in case of 40mhz frequency, cl1 can be supported. note : ? . 3.0v & 3.3v power supply ? lvttl compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (1 & 2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? . burst read single-bit write operation ? dqm for masking ? . auto & self refresh ? . 64ms refresh period (4k cycle). ? . extended temperature operation (-25 c ~ 85 c). ? . 90balls fbga based on 2 pcs of 4mx16 sdram. bank select data input register 1m x 32 1m x 32 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 1m x 32 1m x 32 timing register * samsung electronics reserves the right to change products or specification without notice. the k4s283233f is 134,217,728 bits synchronous high data rate dynamic ram organized as 4 x 1,048,576 words by 32 bits, fabricated with samsung s high performance cmos technology. synchronous design allows precise cycle control with the use of system clock and i/o transactions are possible on every clock cycle. range of operating frequencies, program- mable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications.
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram 90ball(6x15) csp 1 2 3 7 8 9 a dq26 dq24 v ss v dd dq23 dq21 b dq28 v ddq v ssq v ddq v ssq dq19 c v ssq dq27 dq25 dq22 dq20 v ddq d v ssq dq29 dq30 dq17 dq18 v ddq e v ddq dq31 nc nc dq16 v ssq f v ss dqm3 a3 a2 dqm2 v dd g a4 a5 a6 a10 a0 a1 h a7 a8 nc nc ba1 a11 j clk cke a9 ba0 cs ras k dqm1 nc nc cas we dqm0 l v ddq dq8 v ss v dd dq7 v ssq m v ssq dq10 dq9 dq6 dq5 v ddq n v ssq dq12 dq14 dq1 dq3 v ddq p dq11 v ddq v ssq v ddq v ssq dq4 r dq13 dq15 v ss v dd dq0 dq2 pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 11 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable dqm 0 ~ dqm 3 data input/output mask dq 0 ~ 31 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground package dimension and pin configuration < bottom view *1 > < top view *2 > < top view *2 > *2: top view symbol min typ max a 1.35 1.40 1.45 a 1 0.30 0.35 0.40 e - 11.00 - e 1 - 6.40 - d - 13.00 - d 1 - 11.20 - e - 0.80 - j b 0.40 0.45 0.50 z - - 0.10 [unit:mm] 5 2 1 6 3 4 8 9 7 f e d c b j h g a e d d / 2 d 1 e 1 e e/2 a a1 z j b substrate(4layer) k 4 s 2 8 3 2 3 3 f s a m s u n g w e e k #a1 ball origin indicator *1: bottom view m l k r p n
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c) parameter symbol min typ max unit note supply voltage v dd 2.7 3.0 3.6 v v ddq 2.7 3.0 3.6 v input logic high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 capacitance (v dd = 3.0v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 4.0 8.0 pf ras , cas , we , cs , cke, dqm c in 4.0 8.0 pf address c add 4.0 8.0 pf dq 0 ~ dq 31 c out 3.0 6.5 pf 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. note : absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note :
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c) parameter symbol test condition version unit note -75 -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 150 140 130 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 2 ma i cc2 ps cke & clk v il (max), t cc = 2 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 30 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 12 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 6 ma i cc3 ps cke & clk v il (max), t cc = 6 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 50 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 30 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 220 180 170 ma 1 refresh current i cc5 t rc 3 t rc (min) 250 220 210 ma 2 self refresh current i cc6 cke 0.2v -me 2 ma 3 -mn 800 ua 4 1. measured with outputs open. 2. refresh period is 64ms. 3. K4S283233F-Me** 4. K4S283233F-Mn** 5. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq) notes :
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note - 75 -1h -1l row active to row active delay t rrd (min) 15 20 20 ns 1 ras to cas delay t rcd (min) 20 20 24 ns 1 row precharge time t rp (min) 20 20 24 ns 1 row active time t ras (min) 45 50 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 65 70 84 ns 1 last data in to row precharge t rdl (min) 2 clk 2 last data in to active delay t dal (min) 2 clk + trp - last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 cas latency=1 - 0 ac operating test conditions (v dd = 2.7 v ~ 3.6v , t a = -25 to 85 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. notes : 3.0v 1200 w 870 w output 30pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 30pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol - 75 -1h -1l unit note min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 10 1000 10 1000 ns 1 cas latency=2 10 10 12 cas latency=1 - - 25 clk to valid output delay cas latency=3 t sac 5.5 6 6 ns 1,2 cas latency=2 6 6 6 cas latency=1 - - 18 output data hold time cas latency=3 t oh 2 2 2 ns 2 cas latency=2 2 2 2 cas latency=1 - - 2 clk high pulse width t ch 2.5 3 3 ns 3 clk low pulse width t cl 2.5 3 3 ns 3 input setup time t ss 2.5 3 3 ns 3 input hold time t sh 1 1 1 ns 3 clk to output in low-z t slz 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.5 6 6 ns cas latency=2 6 6 6 cas latency=1 - - 18
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 9 ~ a 0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data-in at that same clk in write operation (write dqm latency is 0), but in read operation makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). note :
K4S283233F-M rev. 0.8 nov. 2001 cmos sdram samsung shall not offer for sale or sell either directly or through and third-party proxy, and dram memory products that include "multi-die plastic dram" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top computers for the first three years of five year term of this license. nothing herein limits the rights of samsung to use multi-die plastic dram in other products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or notebook computers, cell phones, televisions or visual monitors) violation may subject the customer to legal claims and also excludes any warranty against infringement from samsung." note :
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